The present invention relates to the field of displaying on-screen-display graphics data on a display device. More particularly, the present invention relates to the field of displaying bitmap animation of on-screen-display graphics data on a display device.
The IEEE 1394-1995 standard, xe2x80x9c1394 Standard For A High Performance Serial Bus,xe2x80x9d is an international standard for implementing an inexpensive high-speed serial bus architecture which supports both asynchronous and isochronous format data transfers. In addition, the IEEE 1394-1995 bus has a universal clock called the cycle timer. This clock is synchronized on all nodes. Isochronous data transfers are real-time transfers which take place based on the universal clock such that the time intervals between significant instances have the same duration at both the transmitting and receiving applications. Each packet of data transferred isochronously is transferred in its own time period. An example of an ideal application for the transfer of data isochronously would be from a video recorder to a television set. The video recorder records images and sounds and saves the data in discrete chunks or packets. The video recorder then transfers each packet, representing the image and sound recorded over a limited time period, during that time period, for display by the television set. The IEEE 1394-1995 standard bus architecture provides multiple independent channels for isochronous data transfer between applications. A six bit channel number is broadcast with the data to ensure reception by the appropriate application. This allows multiple applications to simultaneously transmit isochronous data across the bus structure. Asynchronous transfers are traditional reliable data transfer operations which take place as soon as arbitration is won and transfer a maximum amount of data from a source to a destination.
The IEEE 1394-1995 standard provides a high-speed serial bus for interconnecting digital devices thereby providing a universal I/O connection. The IEEE 1394-1995 standard defines a digital interface for the application thereby eliminating the need for an application to convert digital data to analog data before it is transmitted across the bus. Correspondingly, a receiving application will receive digital data from the bus, not analog data, and will therefore not be required to convert analog data to digital data. The cable required by the IEEE 1394-1995 standard is very thin in size compared to other bulkier cables used to connect such devices in other connection schemes. Devices can be added and removed from an IEEE 1394-1995 bus while the bus is operational. If a device is so added or removed the bus will then automatically reconfigure itself for transmitting data between the then existing nodes. A node is considered a logical entity with a unique address on the bus structure. Each node provides in a standard address space, an identification ROM, a standardized set of control registers and in addition, its own address space.
The IEEE 1394-1995 standard defines a protocol as illustrated in FIG. 1. This protocol includes a serial bus management block 10 coupled to a transaction layer 12, a link layer 14 and a physical layer 16. The physical layer 16 provides the electrical and mechanical connection between a device and the IEEE 1394-1995 cable. The physical layer 16 also provides arbitration to ensure that all devices coupled to the IEEE 1394-1995 bus have arbitrated access to the bus as well as actual data transmission and reception. The link layer 14 provides data packet delivery service for both asynchronous and isochronous data packet transport. This supports both asynchronous data transport, using an acknowledgement protocol, and isochronous data transport, providing an un-acknowledged real-time guaranteed bandwidth protocol for just-in-time data delivery. The transaction layer 12 supports the commands necessary to complete asynchronous data transfers, including read, write and lock. The serial bus management block 10 contains an isochronous resource manager for managing isochronous data transfers. The serial bus management block 10 also provides overall configuration control of the serial bus in the form of optimizing arbitration timing, guarantee of adequate electrical power for all devices on the bus, assignment of the cycle master, assignment of isochronous channel and bandwidth resources and basic notification of errors.
A home audio/video interoperability (HAVi) architecture is defined by xe2x80x9cThe HAVi Architecture: Specification of the Home Audio/Video Interoperability (HAVi) Architecture,xe2x80x9d draft version 0.8n13, Sep. 16, 1998. The HAVi architecture is to be implemented on consumer electronics devices and computing devices. The HAVi architecture provides a set of services which facilitate interoperability and the development of distributed applications on home networks. The HAVi architecture is designed for digital devices coupled together within an IEEE 1394-1995 serial bus network.
The HAVi architecture defines two on-screen-display graphics models, referred to as level 1 and level 2. The level 1 on-screen-display graphics model is a descriptive model in which the target device provides, through a series of commands from the control device, data structures which describe the intended on-screen-display graphics. Using a graphics library applications programming interface, the display device uploads this information and constructs the display graphics, which may or may not look as the target device intended. The level 2 on-screen-display graphics model defines a runtime execution environment, where the display device uploads executable code which runs on the display device itself. This executable code is then used to generate the on-screen-display graphics using facilities provided by the display device. Using the HAVi architecture, a source device such as a digital VCR can generate data which is transmitted to the display device and utilized by the display device to generate the on-screen-display graphics.
A method of and apparatus for bitmap animation and display of on-screen-display graphics utilizes the HAVi architecture and displays the bitmap animation using a clipping region and a visible window. Data for a bitmap image of on-screen-display graphics is generated by a graphics source within a source device. The data is transmitted to a display device including a rendering engine. The bitmap image is then rendered by the display device. A clipping region and visible window are applied to the bitmap image as it is displayed by the display device. Only the portion of the bitmap image corresponding to the logical intersection of the visible window and the clipping region is displayed by the display device. The clipping region, visible window and the bitmap image can be moved in relation to each other through an animation sequence. The bitmap image can also be changed to generate animation within the clipping region. The size, position, path and other attributes of the clipping region are set within a bitmap animation object structure. Data for an object can also be generated by the source device and transmitted to the display device. The object can be moved through an animation sequence when displayed by the display device. Images or animation sequences can be displayed on or in the object.
In one aspect of the present invention, a display through which a rendered image is displayed includes a visible window applied to a first portion of the rendered image and a clipping region through which only a second portion of the rendered image is visible. The clipping region can be moved in relation to the rendered image. The rendered image can be moved in relation to the clipping region. A source device is configured to generate data related to the rendered image, the clipping region and the visible window. The display still further includes a rendering engine coupled to the source device to render the rendered image and apply the clipping region and the visible window. The displayed image is preferably a bitmap image. The rendering engine is preferably coupled to the source device by a high speed serial interface. The data is preferably generated according to HAVi architecture. Alternatively, the data is generated according to the AV/C panel subunit. Preferably, the high speed serial interface is an IEEE 1394 serial bus.
In another aspect of the present invention, a method of generating on-screen-display graphics on a display device includes the steps of generating on-screen-display graphics data at a source device relating to a bitmap image, clipping region and visible window, transmitting the on-screen-display graphics data to the display device, rendering the bitmap image at the display device, applying the clipping region and the visible window to the bitmap image and displaying only a first portion of the bitmap image corresponding to an intersection of the visible window and the clipping region. A second portion of the bitmap a image outside of the intersection of the visible window and the clipping region is masked. The method further includes the step of generating an animation effect by moving the clipping region in relation to the bitmap image. The method also includes the step of generating an animation effect by moving the bitmap image in relation to the clipping region. The method also includes the step of storing the bitmap image at the display device. The source device is preferably coupled to the display device by a high speed serial interface. Preferably, the high speed serial interface is an IEEE 1394 serial bus. The on-screen-display graphics data is generated according to HAVi architecture. Alternatively, the on-screen-display graphics data is generated according to the AV/C panel subunit.
In yet another aspect of the present invention, a method of generating an object on a display device includes the steps of generating on-screen-display graphics data at a source device relating to the object, transmitting the on-screen-display graphics data to the display device, rendering the object at the display device, displaying the object at the display device and generating an animation effect by moving the object along a path prescribed by the on-screen-display graphics data. The method further includes the step of displaying one or more images on the object. The source device is preferably coupled to the display device by a high speed serial interface. Preferably, the high speed serial interface is an IEEE 1394 serial bus. The on-screen-display graphics data is preferably generated according to HAVi architecture. Alternatively, the on-screen-display graphics data is generated according to the AV/C panel subunit.
In still another aspect of the present invention, a system for generating and displaying images includes a source device having a graphics source for generating on-screen-display graphics data relating to a bitmap image, clipping region and visible window and a source interface circuit coupled to the graphics source for transmitting the on-screen-display graphics data and a display device having a display interface circuit coupled to the source interface circuit for receiving the on-screen-display graphics data, a rendering engine coupled to the display interface circuit for receiving the on-screen-display graphics data, rendering the bitmap image and applying the clipping region and the visible window to the bitmap image and a display coupled to the rendering engine for displaying only a first portion of the bitmap image corresponding to an intersection of the visible window and the clipping region. A second portion of the bitmap image outside of the intersection of the visible window and the clipping region is masked. The bitmap image can be moved in relation to the clipping region. The clipping region can be moved in relation to the bitmap image. The display interface circuit is preferably coupled to the source interface circuit by a high speed serial interface. Preferably, the high speed serial interface is an IEEE 1394 serial bus. The on-screen-display graphics data is preferably generated according to HAVi architecture. Alternatively, the on-screen-display graphics data is generated according to the AV/C panel subunit. The system further includes a memory buffer coupled to the rendering engine for storing the bitmap image.